CALL FOR PAPERS

The International Conference on Signal Processing and Communications Systems – SPCS 2016

Website: www.spcs.peccs.org

25 – 27 July, 2016

Lisbon, Portugal

Regular Papers

Paper Submission: February 16, 2016

Authors Notification: May 5, 2016

Camera Ready and Registration: May 19, 2016

Position Papers

Paper Submission: May 2, 2016

Authors Notification: June 6, 2016

Camera Ready and Registration: June 17, 2016

Workshops

Workshop Proposal: February 26, 2016

Doctoral Consortium

Paper Submission: May 30, 2016

Authors Notification: June 7, 2016

Camera Ready and Registration: June 17, 2016

Special Sessions

Special Session Proposal: March 8, 2016

Tutorials, Demos and Panels Proposals

March 31, 2016

Sponsored by:

INSTICC – Institute for Systems and Technologies of Information, Control and Communication

Sponsored by:

INSTICC – Institute for Systems and Technologies of Information, Control and Communication

INSTICC is Member of:

WfMC – Workflow Management Coalition

In Cooperation with:

ACM – Association for Computing Machinery

SIGAPP – Special Interest Group on Applied Computing

EUROMICRO

IET – The Institution of Engineering Technology

EURASIP – The European Association for Signal Processing

Logistics Partner:

SCITEVENTS – Science and Technology Events

SPCS is part of PECCS, the 6th International Conference on Pervasive and Embedded Computing and Communication Systems.

Registration to PEC allows free access to all other PECCS conferences.

PECCS 2016 will be held in conjunction with PhyCS 2016.

PECCS KEYNOTE LECTURE

Siegfried Benkner, University of Vienna, Austria
Maria R. Ebling, IBM T.J. Watson Research Center, United States

PUBLICATIONS

All accepted papers will be published in the conference proceedings, under an ISBN reference, on paper and on CD-ROM support.

SCITEPRESS is a member of CrossRef (http://www.crossref.org/) and every paper is given a DOI (Digital Object Identifier).

All papers presented at the conference venue will be available at the SCITEPRESS Digital Library.

It is planned to publish a short list of revised and extended versions of presented papers with Springer in a CCIS Series book .

The proceedings will be submitted for indexation by Thomson Reuters Conference Proceedings Citation Index (ISI), INSPEC, DBLP, EI (Elsevier Engineering Village Index) and Scopus.

AWARDS

The awards will be announced and bestowed at the conference closing session.

Please check the websites for further information: http://www.spcs.peccs.org/BestPaperAward.aspx

PECCS CONFERENCE CHAIR

César Benavente-Peces, Universidad Politécnica de Madrid, Spain

PROGRAM CHAIR

Andreas Ahrens, Hochschule Wismar, University of Technology Business and Design, Germany

CONFERENCE AREAS:

Each of these topic areas is expanded below but the sub-topics list is not exhaustive. Papers may address one or more of the listed sub-topics, although authors should not feel limited by them. Unlisted but related sub-topics are also acceptable, provided they fit in one of the following main topic areas:

1. 1. IMAGE PROCESSING
2. 2. AUDIO AND SPEECH SIGNAL PROCESSING
3. 3. BIOMEDICAL SIGNAL PROCESSING
4. 4. COMMUNICATION SYSTEMS

AREA 1: IMAGE PROCESSING

• Adaptive Systems
• Detection and Estimation
• Image and Multidimensional Signal Processing
• Image Processing
• Multimedia Communication Systems
• Time-frequency Analysis
• Wavelet Signal Processing

AREA 2: AUDIO AND SPEECH SIGNAL PROCESSING

• Adaptive Systems
• Audio and Speech Signal Processing
• Detection and Estimation
• Digital Filter Design and Implementation
• Multimedia Communication Systems
• Time-frequency Analysis
• Wavelet Signal Processing

AREA 3: BIOMEDICAL SIGNAL PROCESSING

• Biomedical Signal Processing
• Detection and Estimation
• Remote Sensing and Signal Processing
• Time-frequency Analysis
• Biomedical Sensors

AREA 4: COMMUNICATION SYSTEMS

• Antennas and Propagation
• Channel Measurements and Modeling
• Coding and Modulation Techniques
• Communication Systems
• Diversity Techniques
• Green communications
• MIMO – Theory and Trials
• OFDM Technology
• Optical Communications and Networks
• Signal Processing in Communications
• Space-time cOding
• Spread Spectrum and CDMA Systems
• Ultra Wide-Band Communications
• Wireless and Mobile Networks

PROGRAM COMMITTEE

http://www.spcs.peccs.org/ProgramCommittee.aspx

SPCS Secretariat

Address: Av. D. Manuel I, 27A, 2º esq.
2910-595 Setúbal – Portugal
Tel.: +351 265 520 184
Fax: +351 265 520 186

e-mail: spcs.secretariat@insticc.org

Web: http://www.spcs.peccs.org/

ACM ToDAES special section – Call for Papers
IDEA: Integrating Dataflow, Embedded computing, and Architecture

Special Section Guest Editors:
Twan Basten (Eindhoven University of Technology), Orlando Moreira (Intel), Robert de Groote (Twente University)
contact: acm.todaes.idea@gmail.com

Important Dates:
– January 8, 2016 – Paper submission deadline
– March 4, 2016 – First round of reviews complete, notification of authors
– May 1, 2016 – Submission of revised versions
– June 15, 2016 – Second round of reviews complete, final acceptance notifications
– Summer/Fall 2016 – Final versions due and special section publication

Scope:
The dataflow model of computation (with SDF, CSDF, and DDF as primary representatives) offers a powerful perspective on parallel computations that may be conditioned in terms of data dependencies. It dates back to the nineteen sixties and has applications in the design of real-time stream-processing systems, especially in the area of digital signal processing. The dataflow model of computation fits the characteristics of embedded and cyber-physical systems, with a strong emphasis on both the functional and temporal aspects of data processing systems. Dataflow is gaining renewed popularity, stimulated by the trend towards multi-core and multi-processor architectures, with an influx of work ranging from using dataflow as a programming paradigm, for performance analysis, or for design optimization. Topics of interest for the special section include, but are not limited to:

• Dataflow architectures and dataflow as a programming paradigm for multi-core and multi-processor systems, for embedded systems and for cyber-physical systems.
• Tools for compilation, evaluation, optimization or synthesis of applications for heterogeneous and homogeneous multi-processor systems.
• Real-time scheduling, analysis, response time modeling, schedule synthesis. Variants of the dataflow model of computation, capturing e.g. dynamic execution behavior, stochastic dataflow.
• Dataflow theory, relations between dataflow and other models of computation, relations between dataflow variants.
• Dataflow in multi-disciplinary design, applications of dataflow in control, integrating dataflow and control theory.
• Case studies of general interest describing the application of dataflow in embedded computing and cyber-physical systems, ranging from automotive systems, and avionics, to high-tech systems, smart buildings and smart grids.

Submission Guidelines:
Submissions should follow the usual ToDAES guidelines. Submissions go through https://mc.manuscriptcentral.com/todaes. When asked “Is this manuscript a candidate for a special issue?”, mark “Yes” to ensure that the paper is allocated to the guest editors of the special section.

IDEA 2016 workshop @ CPS week:
To further stimulate discussion in the dataflow community, we are organizing a workshop at CPS week in Vienna, April 11, 2016. Authors of papers submitted to the IDEA ToDAES special section that successfully pass the first round of reviews are invited to present their work at the workshop. Participation in the workshop will increase the visibility of the presented work and increase quality through the discussion at the workshop. See http://caes.ewi.utwente.nl/idea2016 for more information about the workshop, including information on how to express interest to present the submitted work. Presentation and discussion at the workshop is optional and will not in any way influence acceptance for the special section.

IEEE 2016 The 2nd International Conference on Control, Automation and Robotics (ICCAR 2016)
Hong Kong, April 28–30, 2016.
Conference official website: http://iccar.org/.

ICCAR 2016 conference proceedings will be published by IEEE Conference Publication, which would be indexed by <<IEEE Xplore and Ei Compendex>>.

ICCAR 2016 is in the IEEE conference list.
http://www.ieee.org/conferences_events/conferences/search/index.html?KEYWORDS=iccar&CONF_SRCH_RDO=conf_date&RANGE_FROM_DATE=&RANGE_TO_DATE=®ION=ALL&COUNTRY=ALL&RowsPerPage=10&PageLinkNum=10&ActivePage=1&SORTORDER=desc&SORTFIELD=start_date

Publication and Indexing History of ICCAR:
ICCAR 2015, Singapore, May 20-22, 2015.
Publication: IEEE Conference Proceedings
Online: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?reload=true&punumber=7153096

Keynote and Plenary Speakers
Prof. Wei-Hsin Liao, The Chinese University of Hong Kong. Excellent editor of SPIE, IEEE fellow
Prof. Felix T. S. Chan, The Hong Kong Polytechnic University.
Prof. Maode Ma, Nanyang Technological University, Singapore. IEEE senior editor, IEEE fellow
Dr. GirijaChetty University Of Canberra, Canberra, Australia

Contact:
Cindy Lau/ +1-562-606-1057/ iccar@sciei.org

International Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems  (ERMAVSS)

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			Call for Papers

10th International Symposium on Networks-on-Chip (NOCS 2016)
August 31 - September 2, 2016
Nara, Japan
		http://www.arc.ics.keio.ac.jp/nocs16
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	The International Symposium on Networks-on-Chip (NOCS) is the
premier event dedicated to interdisciplinary research on on-chip,
chip-scale, and multichip package scale communication technology,
architecture, design methods, applications and systems. NOCS brings
together scientists and engineers working on NoC innovations and
applications from inter-related research communities, including
computer architecture, networking, circuits and systems, packaging,
embedded systems, and design automation. Topics of interest include,
but are not limited to:

NoC Architecture and Implementation:

1. Network architecture (topology, routing, arbitration)
2. NoC Quality of Service
3. Timing, synchronous/asynchronous communication
4. NoC reliability issues
5. Network interface issues
6. NoC design methodologies and tools
7. Signaling & circuit design for NoC links

NoC Analysis and Verification:

1. Power, energy & thermal issues (at the NoC, un-core and/or system-level)
2. Benchmarking & experience with NoC-based hardware
3. Modeling, simulation, and synthesis of NoCs
4. Verification, debug & test of NoCs
5. Metrics and benchmarks for NoCs

Novel NoC Technologies:

1. New physical interconnect technologies, e.g., carbon nanotubes, wireless
   NoCs, through-silicon, etc. 
2. NoCs for 3D and 2.5D packages
3. Package-specific NoC design
4. Optical, RF, & emerging technologies for on-chip/in-package interconnects

NoC Application:

1. Mapping of applications onto NoCs
2. NoC case studies, application-specific NoC design
3. NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
4. NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
5. Scalable modeling of NoCs

NoC at the Un-Core and System-level:
 
1. Design of memory subsystem (un-core) including memory controllers,
   caches, cache coherence protocols & NoCs
2. NoC support for memory and cache access
3. OS support for NoCs
4. Programming models including shared memory, message passing and
   novel programming models
5. Issues related to large-scale systems (datacenters, supercomputers)
   with NoC-based systems as building blocks

On-Chip Communication Optimization:

1. Communication efficient algorithms
2. Multi/many-core communication workload characterization & evaluation
3. Energy efficient NoCs and energy minimization

	Electronic paper submission requires a full paper, up to 8
double-column IEEE format pages, including figures and references.
The program committee in a double-blind review process will evaluate
papers based on scientific merit, innovation, relevance, and presentation.
	Submitted papers must describe original work that has not been
published before or is under review by another conference or journal
at the same time. Each submission will be checked for any significant
similarity to previously published works or for simultaneous
submission to other archival venues, and such papers will be rejected. 
Proposals for special sessions, tutorials, and demos are invited. Paper 
submissions and demo proposals by industry researchers or engineers to
share their experiences and perspectives are also welcome.
	Please see the detailed submission instructions for paper
submissions, special session, tutorial, and demo proposals at the
submission page. Further information is available via:
http://www.arc.ics.keio.ac.jp/nocs16

Important Dates:

Abstract registration deadline		February 5th, 2016
Full paper submission deadline		February 12th, 2016
Notification of acceptance		April 8th, 2016
Final version due			May 18th, 2016

Organizing Committee

General Co-Chairs:
- Hideharu Amano (Keio University, Japan) 
- Partha Pratim Pande (Washington State University, USA) 
Technical Program Co-Chairs:
- Hiroki Matsutani (Keio University, Japan) 
- Sriram Vangal (Intel, USA) 
Publicity Co-Chairs:
- John Kim (Korea Advanced Institute of Science and Technology, Korea) 
- Turbo Majumder (Intel, USA) 
- Maurizio Palesi (Kore University, Italy) 
Publication Chair:
- Umit Ogras (Arizona State University, USA) 
Special Sessions Co-Chairs:
- Michihiro Koibuchi (National Institute of Informatics, Japan) 
- Sudeep Pasricha (Colorado State University, USA) 
Tutorial Chair:
- Paul Bogdan (University of Southern California, USA) 
Finance Chair:
- Ikki Fujiwara (National Institute of Informatics, Japan) 
Registration Chair:
- Takashi Nakada (University of Tokyo, Japan) 
Local Arrangements Chair:
- Shinya Takamaeda (Nara Institute of Science and Technology, Japan) 
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