BDML 2018
2018 International Conference on Big Data and Machine Learning
Nagoya, Japan
November 23–25, 2018
http://www.bdml.org/
Submission Deadline: July. 5, 2018
Notification of Acceptance: July. 25, 2018

Call for Paper:
Network architectures and algorithms

Distributed systems design, implementation and application

Enterprise, datacenter, and storage area networks

SDN, NFV, and network programming

Experimental results from operational networks or network applications

More Information: http://www.bdml.org/cfp.html

Publication:
All submissions will be blind reviewed by the Program Committee on the basis of technical quality, relevance to conference topics of interest, originality, significance, and clarity. All accepted and presented papers will be published in International Conference Proceedings Series, which will be indexed by Ei Compendex and Scopus after the conference.

Venue:
Nagoya Institute of Technology, Gokiso-cho, Showa-ku, Nagoya 466-8555, Japan

Agenda Overview:
November 23, 2018 Registration
November 24, 2018 Keynote Speech and Session Presentations
November 25, 2018 One Day Tour in Nagoya

Submission Methods:
Full Paper (publication and oral presentation)
Abstract (oral presentation only)
Electronic Submission System (.pdf)
http:https://easychair.org/conferences/?conf=bdml2018

Call for Papers

ECYPS’2018 – the 6^th EUROMICRO/IEEE Workshop on Embedded and Cyber-Physical Systems will be held in the scope of MECO’2018 – the 7^th Mediterranean Conference on Embedded Computing, in Budva, Montenegro, June 10-14, 2018. Cyber-physical systems (CPS) are smart compound systems engineered through seamless integration of embedded information processing sub-systems and physical sub-systems. The vision of smart systems connected and collaborating through various interfaces and communication media to form the global Internet of Things (IoT) is not a science-fiction anymore, but is quickly becoming an actual reality. The smart collaborating CPS with important applications in virtually all economic and social segments will have enormous economic and societal impact. ECYPS’2018 mainly focuses on CPS for modern (mobile) applications that require high-performance or low energy consumption, as well as, high safety, security and reliability. It addresses the applications, specification, validation, architectures, technology, hardware, software, design methodology and EDA tools for such systems. Its target participants are academic researchers and teachers; industrial researchers, developers and decision-makers; and Ph.D. students. It gives an excellent opportunity to disseminate fresh research results from European, international and other R&D projects. The topics of interest include, but are not limited to, the following:

ñ advanced applications and case studies of systems in consumer appliances,  healthcare, personal assistance, environmental and safety monitoring, industrial and leaving-space automation, transportation, automotive, aerospace, aviation, energy generation,  communications, tele-operation,  control, robotics, infrastructure, etc.

ñ mobile, autonomous, wearable and implantable systems

ñ development platforms and tools for CPS

ñ deep-learning and AI for CPS

ñ application/software modeling, analysis, parallelization and mapping for high-performance and low-energy computing

ñ multi-domain modeling, analysis, synthesis, simulation, integration and validation of heterogeneous systems

ñ multi-objective and multi-domain optimization and co-design of heterogeneous systems

ñ advanced processors, MPSoCs, SiPs, sensors, actuators and MEMS for CPS

ñ sensor-based (distributed, networked) monitoring and control

ñ sub-system arrangement and communication in complex heterogeneous systems

ñ safety, security and reliability of complex heterogeneous systems

ñ IoT, and cloud, fog, dew and edge computing

Venue: ECYPS’2018 will be held in Hotel Budva**** (http://www.hotelbudva.me/) Budva (https://www.visit-montenegro.com/main-cities/budva/), Montenegro (http://www.visit-montenegro.com/).

Budva is a 3500 years old town located at the Adriatic Sea coast of Montenegro. It is a popular touristic destination. Budva’s main attractions are the charm of its Old Town, its beautiful natural environment, 35 clean sandy beaches, and proximity to many famous touristic attractions as Kotor, Boka Kotorska, Sveti Stefan, Dubrovnik, and several national parks. It is also a place of various cultural events, clubs and many restaurants with excellent mediterranean kitchen. Budva is well connected with European cities by sea, road, air and train.

Submission of papers: Prospective authors are invited to submit full-length, four-page papers, strictly according to the IEEE Conference Standards and via http://embeddedcomputing.me.

Conference quality: Conference content will be submitted for inclusion into IEEE Xplore as well as other Abstracting and Indexing (A&I) databases. In particular, ECYPS is covered by SCOPUS, Web of Science, Google Scholar, Research Gate, etc. Extended versions of selected papers from ECYPS will be published in the Elsevier/Euromicro journal of Microprocessors and Microsystems(MICPRO) having the 2016 Impact Factor as high as 1.025.

Accompanying events: ECYPS’2018 will be held in the scope of MECO’2018 (the 7th Mediterranean Conference on Embedded Computing) which will host several special sessions, workshops and dissemination of international projects. Proposals of accompanying workshops/sessions/dissemination should be submitted to Radovan Stojanović (stox@ac.me).

Important Deadlines:

January 28, 2018, Paper submission deadline

February 25, 2018, Acceptance/rejection notification

March 10, 2018, Final paper submission and author registration deadline

May 05, 2018, Registration deadline

Fees: The participation fees of MECO and ECYPS are low to encourage participation of young scientists and colleagues from developing countries.

Conference Chairs:

Lech Jóźwiak, Eindhoven University of Technology, Netherlands

Radovan Stojanović, University of Montenego, Montenegro

Scientific Committee:

Koen Bertels, Delft University of Technology, Netherlands

Zlatan Car, University of Rijeka, Croatia

Victor Goulart, Kyushu University, Japan

Yervant Zorian. Synopsys, USA

Miguel Figueroa, University of Concepcion, Chile

Roberto Giorgi, University of Siena, Italy

Erwin Grosspietsch, Euromicro, Germany

Ilker Hamzaoglu, Sabanci University, Turkey

Lech Jóźwiak, EUT, Netherlands

Paris Kitsos, Open Hellenic University, Patras, Greece

Akash Kumar, National Univ. Singapore, Singapore

Francesco Leporati, University of Pavia, Italy

Menno Lindwer, Intel, Netherlands

Jan Madsen, Technical University of Denmark, Denmark

Veljko Milutinovic, University of Belgrade, Serbia

Nadia Nedjah, State University of Rio de Janeiro, Brazil

Smail Niar, University of Valenciennes, France

Horácio .C Neto, Technical University of Lisbon, Portugal

Jari Nurmi, Tampere University of Technology, Finland

Alex Orailoglu, University of California at San Diego, USA

Sri Parameswaran, UNSW, Australia

Adam Postula, University of Queensland, Australia

Peter Puschner, Vienna Univ. of Technology, Austria

Davide Quaglia, University of Verona, Italy

Majid Sarrafzadeh, UCLA, California, USA

Karolj Skala, Ruđer Bošković Institute, Croatia

Radovan Stojanović, University of Montenegro, Montenegro

Ioannis Sourdis, Chalmers Univ. of Technology, Sweden

Alice M. Tokarnia, State University of Campinas, Brazil

Heinrich Vierhaus, Brandenburg Uni. of Technology, Germany

Eugenio Villar, University of Cantabria, Spain

Arda Yurdakul, Bogazici University, Turkey

Andrej Žemva, University of Ljubljana, Slovenia

Local Organizing Committee:

Budimir Lutovac, University of Montenegro, Chair

Dmitry Tarasov, MANT, Montenegro, Co-Chair

Marko Kaludjerović, MANT, Montenegro

The 14^th IEEE Workshop on Silicon Errors in Logic – System Effects SELSE 2018 (http://www.selse.org)

April 3 – April 4, 2018, Boston, Massachusetts, USA

Important dates:

∙         Abstract submission (mandatory):                      December 20, 2017

∙         Paper submission (for registered abstracts):     January 12, 2018

∙         Authors notification:                                               February 16, 2018

∙         Camera-ready submission:                                    March 1, 2018

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching especially in safety-critical applications like aerospace and automotive. Growing concern about transient errors, unstable storage cells, and the effects of aging are influencing system and application design. While the computational capabilities of emerging logic and memory device technologies are attractive for several safety-critical applications and new computing philosophies like deep learning become popular, they introduce several reliability challenges that need to be addressed. Additionally, reliability is a key issue for large-scale systems, such as those in data centers and cloud computing infrastructure. This year, we also welcome papers on the system security issues as they relate to and impact system reliability.

The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions. SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also solicited.

Areas

Key areas of interest are (but not limited to):

• Technology trends and their impact on error rates.
• New error mitigation techniques.
• Error handling protocols (higher-level protocols for robust system design).
• Characterizing the overhead and design complexity of error mitigation techniques.
• Case studies describing the tradeoff analysis for reliable systems.
• System-level models: derating factors and validation of error models.
• Experimental data on failures in current and emerging technologies and applications
• Characterization of reliability of systems deployed in the field and mitigation of issues.
• Software-level impact of hardware failures.
• Software frameworks for resilience.
• Impact of machine learning components on system resilience.
• Resilient accelerator-rich systems.
• Inexact or approximate computing as it relates to system errors.
• (New) Cross-layer resilience techniques.
• (New) System security issues that impact and interact with system reliability.

Concurrency to System Design (ACSD 2017)

Zaragoza, Spain, June 28-30, 2017
http://pn2017.unizar.es

*IMPORTANT DATES*

submission deadline (abstracts):    January 13, 2017
submission deadline (papers):       January 20, 2017
notification of acceptance:         March 17, 2017
camera-ready submission deadline:   April 15, 2017
conference sessions:                June 26-30, 2017

*CONFERENCE SCOPE*

The conference aims at cross-fertilizing both theoretical and applied research
about formal approaches (in a broad sense) to designing computer systems that
exhibit some kind of concurrent behaviour. In particular, the following topics
are of interest:

* Formal models of computation and concurrency for the above systems and
problems, like data-flow models, communicating automata, Petri nets,
process algebras, graph rewriting systems, state charts, MSCs, modal and
temporal logics
* Compositional design principles like modular synthesis, distributed
simulation and implementation, distributed control, adaptivity,
supervisory control
* Algorithms and tools for concurrent systems, ranging from programming
languages to algorithmic methods for system analysis and construction,
including model checking, verification, and static analysis techniques
as well as synthesis procedures
* Synchronous and asynchronous systems on all design levels:
polychronous systems, endochronous systems, globally asynchronous locally
synchronous systems
* Cyber-physical systems, hybrid systems, networked systems, and networks in
biological systems
* High-performance computer architectures like many-core processors,
networks on chip, graphics processing units, instruction-level parallelism,
dataflow architectures,  up to ad-hoc, mobile, and wireless networks
* Memory consistency models for multiprocessor and multicore architectures,
replicated data, including software and hardware memory models,
DRAM scheduling, cache coherency, memory-aware algorithms
* Real-time aspects, including hard real-time requirements, security and
safety-critical issues, functional and timing verification
* Implementation aspects like resource management, including task and
communication scheduling, network-, memory-, and power-management,
energy/power distribution, fault-tolerance, quality of service,
scalability, load balancing, power proportionality
* Design principles for concurrent systems, in particular hardware/software
co-design, platform-based design, component-based design, energy-aware
design, refinement techniques, hardware/software abstractions,
cross-layer optimization
* Business process modelling, workflow execution systems,
process (de-)composition, inter-organizational and heterogeneous workflow
systems, systems for computer-supported collaborative work, web services
* Case studies of general interest, from industrial applications to consumer
electronics and multimedia, automotive systems, (bio-)medical applications,
neuromorphic applications, internet (of things) and grid computing,
to gaming applications.

*PAPER SUBMISSION*

ACSD seeks papers describing original work which has not been previously published
and is not under review for publication elsewhere. All files must be prepared
using the latest IEEE Computer Society conference proceedings guidelines
(8.5″ x 11″ two-column format). The page limit for regular papers is 10 pages.

In addition to regular submissions, there will be a tools section. Tools will be
presented at the conference in an interactive session. Related papers describe a
tool, its functionality and interfaces as well as the underlying algorithms and
implementation aspects. These tool papers are limited to 6 pages.

Conference proceedings will be published on IEEE Xplore Digital Library. Accepted
regular and tool papers will be included in the conference proceedings. At least
one authors of each accepted contribution is expected to present the paper or
tool at the conference, and will be required to sign the IEEE copyright release
forms.

Several papers will be considered for publication in extended and revised form
in a special issue of a journal. All papers have to be submitted via EasyChair: https://easychair.org/conferences/?conf=acsd2017

STEERING COMMITTEE
Alex Yakovlev, UK (chair)
Alex Kondratyev, USA
Benoit Caillaud, France
Luciano Lavagno, Italy
Jordi Cortadella, Spain
Antti Valmari, Finland
Jörg Desel, Germany

PROGRAM COMMITTEE CHAIRS
Alex Legay, France
Klaus Schneider, Germany

========================================================================
Call-for-Papers
IEEE T-SUSC Special Issue on Low-Power Dependable Computing (LPDC)
https://www.computer.org/web/tsusc
========================================================================
Submission deadline (extended): Jan. 31, 2017
========================================================================

With the continuous technology scaling and miniaturization of computing systems, faults become more common and it is imperative for most modern computing systems to deploy various fault-tolerance techniques. Traditionally, fault tolerance is achieved in general through various error reduction, detection and recovery techniques at different levels (for instance, circuit, architecture, operating systems, compiler and application software) in the systems. On the other hand, fault-tolerance does not come for free, and generally has power/energy/temperature overheads, which warrants careful consideration since power/energy is a first-class system resource and has been emerging as a significant limiting factor for multicore scaling. In particular, understanding the interdependencies between reliability and power are important to consider, e.g., high power consumption may lead to elevated temperature that can further aggravate reliability. In response to these challenges, this special issue seeks original contributions on novel and bold ideas to achieve low-power dependable computing (LPDC).

Topics of Interests: This issue considers the development of models, algorithms and techniques at all levels (from circuits to software) for all components (from memory to computation) from all modern computing systems (from battery-powered embedded systems to large scale reliable servers) to enable energy efficiency and fault tolerance. The topics of interest include, but are not limited to, the following:

* Energy-efficient redundant circuit design
* Energy-efficient fault-tolerant architecture
* Compilation techniques for reliability and low-power
* Runtime management and scheduling algorithms for energy-efficiency and fault tolerance
* Low-power reliable memory and storage systems
* Low-power and reliable on-chip networks and communication
* Mitigating reliability threats (aging, soft errors, process variations) in Dark Silicon chips
* Emerging paradigms for low-power and dependable computing (e.g., approximate computing)
* Case studies on low-power dependable systems

Instructions for Authors: The special issue opens for all submissions.  Submitted papers should not have been previously published nor be currently under consideration for publication elsewhere. Previously published conference and workshop papers may only be submitted if the paper is substantially extended with at least 30% new material, where the extension requirement of 30% is not in textual volume but in novelty. Active researchers/experts in related areas will be invited for contributions. Authors of accepted papers in the Third Workshop on Low-Power Dependable Computing (LPDC), to be held with International Green and Sustainable Computing (IGSC) in November 2016, will also be invited to submit their extended work. All submissions will go through the same review process and will be treated equally in their consideration for publication.

Papers should be submitted via the Manuscript Central website (https://mc.manuscriptcentral.com/tsusc-cs) and should follow IEEE T-SUSC author guidelines (https://www.computer.org/web/tsusc/author), where the page limit is 14 (including figures and references). Moreover, please indicate that you are submitting to the Special issue on Low-Power Dependable Computing (LPDC) on the first page and in the field “Author’s Cover Letter:” in Manuscript Central.

Any questions on this special issue should be addressed to Dr. Dakai Zhu at dakai.zhu@utsa.edu .

Important Dates:

* Submission deadline (extended):     Jan. 31, 2017
* Preliminary notification:         Apr. 1, 2017
* Revision deadline:             May 15, 2017
* Final notification:             Jul. 15, 2017
* Final manuscript due:         Aug. 1, 2017
* Publication:                 Dec. 2017

Guest Co-Editors:

Dr. Dakai Zhu,         University of Texas at San Antonio, USA
Dr. Muhammad Shafique,     Vienna University of Technology (TU Wien), Austria
Dr. Sudeep Pasricha,         Colorado State University, USA
Dr. Man Lin,             St. Francis Xavier University, Canada