2016 2nd International Conference on Data Mining, Electronics and Information Technology (DMEIT’16) Jan. 23-24, 2015 Patong Beach, Phuket (Thailand) Deadline of New Full Paper/Poster/Abstract Submissions: Nov. 25, 2015 The Proceedings of the Conference will be published by Emirates Research Publishing (ERPUB) and will be will be archived in ERPUB’s Digital Library. Each Paper will be assigned Digital Object Identifier (DOI) from CROSSREF. Paper Page Limit: Regular Papers: 8 pages, including all figures, tables, and references Topics of interest for submission include any topics on related to: – Artificial Intelligence – Bioinformatics – Computer Science & Engineering – Communication Engineering and Mobile Computing – Data Mining – Decision trees/rule learners – E-commerce – Electrical and Control Engineering – Energy and Renewable Energy – Evolutionary computation/meta heuristics – Electronics and Instrumentation Engineering – Machine Learning – Artificial Neural Networks – Classification Algorithms – Image Processing – Information Technology SUBMISSION METHODS 1. Electronic Submission System; (.doc/.docx/.pdf formats): http://eaceee.org/paper_submission.php OR 2. Through Email at: ed@eaceee.org The template can be downloaded using the link: Conference Paper Template DOWNLOAD (.doc): http://erpub.org/ckfinder/userfiles/files/ERPUB%20Template(1).doc Enquiries: ed@eaceee.org Web address: http://dmeit.eaceee.org/ Sponsored by: EACEEE CONFERENCE VENUE THE KEE Resort & Spa Hotel Address : 152/1 Thaveewong Rd., Patong Beach, Kathu, Phuket 83150 Thailand Tel : 076 335 888 Fax : 076 335 808 Website : www.thekeeresort.com

 

*********************************************************************
			Call for Papers

10th International Symposium on Networks-on-Chip (NOCS 2016)
August 31 - September 2, 2016
Nara, Japan
		http://www.arc.ics.keio.ac.jp/nocs16
*********************************************************************

	The International Symposium on Networks-on-Chip (NOCS) is the
premier event dedicated to interdisciplinary research on on-chip,
chip-scale, and multichip package scale communication technology,
architecture, design methods, applications and systems. NOCS brings
together scientists and engineers working on NoC innovations and
applications from inter-related research communities, including
computer architecture, networking, circuits and systems, packaging,
embedded systems, and design automation. Topics of interest include,
but are not limited to:

NoC Architecture and Implementation:

1. Network architecture (topology, routing, arbitration)
2. NoC Quality of Service
3. Timing, synchronous/asynchronous communication
4. NoC reliability issues
5. Network interface issues
6. NoC design methodologies and tools
7. Signaling & circuit design for NoC links

NoC Analysis and Verification:

1. Power, energy & thermal issues (at the NoC, un-core and/or system-level)
2. Benchmarking & experience with NoC-based hardware
3. Modeling, simulation, and synthesis of NoCs
4. Verification, debug & test of NoCs
5. Metrics and benchmarks for NoCs

Novel NoC Technologies:

1. New physical interconnect technologies, e.g., carbon nanotubes, wireless
   NoCs, through-silicon, etc. 
2. NoCs for 3D and 2.5D packages
3. Package-specific NoC design
4. Optical, RF, & emerging technologies for on-chip/in-package interconnects

NoC Application:

1. Mapping of applications onto NoCs
2. NoC case studies, application-specific NoC design
3. NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
4. NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
5. Scalable modeling of NoCs

NoC at the Un-Core and System-level:
 
1. Design of memory subsystem (un-core) including memory controllers,
   caches, cache coherence protocols & NoCs
2. NoC support for memory and cache access
3. OS support for NoCs
4. Programming models including shared memory, message passing and
   novel programming models
5. Issues related to large-scale systems (datacenters, supercomputers)
   with NoC-based systems as building blocks

On-Chip Communication Optimization:

1. Communication efficient algorithms
2. Multi/many-core communication workload characterization & evaluation
3. Energy efficient NoCs and energy minimization

	Electronic paper submission requires a full paper, up to 8
double-column IEEE format pages, including figures and references.
The program committee in a double-blind review process will evaluate
papers based on scientific merit, innovation, relevance, and presentation.
	Submitted papers must describe original work that has not been
published before or is under review by another conference or journal
at the same time. Each submission will be checked for any significant
similarity to previously published works or for simultaneous
submission to other archival venues, and such papers will be rejected. 
Proposals for special sessions, tutorials, and demos are invited. Paper 
submissions and demo proposals by industry researchers or engineers to
share their experiences and perspectives are also welcome.
	Please see the detailed submission instructions for paper
submissions, special session, tutorial, and demo proposals at the
submission page. Further information is available via:
http://www.arc.ics.keio.ac.jp/nocs16

Important Dates:

Abstract registration deadline		February 5th, 2016
Full paper submission deadline		February 12th, 2016
Notification of acceptance		April 8th, 2016
Final version due			May 18th, 2016

Organizing Committee

General Co-Chairs:
- Hideharu Amano (Keio University, Japan) 
- Partha Pratim Pande (Washington State University, USA) 
Technical Program Co-Chairs:
- Hiroki Matsutani (Keio University, Japan) 
- Sriram Vangal (Intel, USA) 
Publicity Co-Chairs:
- John Kim (Korea Advanced Institute of Science and Technology, Korea) 
- Turbo Majumder (Intel, USA) 
- Maurizio Palesi (Kore University, Italy) 
Publication Chair:
- Umit Ogras (Arizona State University, USA) 
Special Sessions Co-Chairs:
- Michihiro Koibuchi (National Institute of Informatics, Japan) 
- Sudeep Pasricha (Colorado State University, USA) 
Tutorial Chair:
- Paul Bogdan (University of Southern California, USA) 
Finance Chair:
- Ikki Fujiwara (National Institute of Informatics, Japan) 
Registration Chair:
- Takashi Nakada (University of Tokyo, Japan) 
Local Arrangements Chair:
- Shinya Takamaeda (Nara Institute of Science and Technology, Japan) 
*********************************************************************

ICAC 2016 2nd Call-for-Papers
http://icac2016.uni-wuerzburg.de/

13th IEEE International Conference on Autonomic Computing (ICAC 2016)
Wuerzburg, Germany, July 19-22, 2016

In cooperation with USENIX and SPEC

CONFERENCE PATRONS
SAP, Huawei, Hewlett Packard Enterprise, Google, Microsoft

WORKSHOPS
* 4th International Workshop on Self-aware Internet of Things (Self-IoT)
* 2nd Workshop on Distributed Adaptive Systems
* 3rd Workshop on Self-Improving System Integration (SISSY)
* 11th International Workshop onModels@run.time
* 11th International Workshop on Feedback Computing

___________________________________________________________________
IMPORTANT DATES

Abstract Submission:            January 14, 2016
Paper Submission:               January 21, 2016
Author Notification:            April 15, 2016
Final Manuscript:               May 1, 2016
Conference:                     July 19-22, 2016

Poster/Demo Proposals Due:              March 30, 2016
Workshop Proposals:                     November 6, 2015
Doctoral Symposium Submissions: January 31, 2016
___________________________________________________________________

SCOPE AND TOPICS

ICAC is the leading conference on autonomic computing, its foundations,
principles, engineering, technologies, and applications. Nowadays,
complex systems of all types, like large-scale data centers, cloud computing
infrastructures, cyber-physical systems, the internet of things, and similar,
are increasingly complex, involving many active, interconnected components
requiring careful coordination. Being impossible for a human to manage
such systems, the autonomic computing paradigm with its support for
self-management capabilities becomes increasingly indispensable
for the components of our IT world.

The conference seeks latest research advances on science and engineering
concerning all aspects of autonomic computing, including but not limited to
the following main research topics:

* Foundations
– Fundamental science and theory of autonomic computing systems and feedback
control for software, self-awareness and self-expression
– Algorithms, such as AI, machine learning, control theory, operations
research, probability and stochastic processes, queueing theory, rule-based
systems, biological-inspired techniques, and socially-inspired techniques
– Formal models and analysis of self-management, emergent behavior,
uncertainty, self-organization, self-awareness, trustworthiness

* Resource Management in Data Centers
– Hypervisors, operating systems, middleware, and platforms for self-managing
data centers and cloud infrastructures
– Sensing, energy efficiency, and resource adaptation
– Autonomic components, such as multi-core servers, storage, networking, and
hardware accelerators
– Applications and case studies of end-to-end design and implementation of
systems for resource management

* Cyber-Physical Systems (CPS) and Internet of Things (IoT)
– System architectures OS, services, middleware, and protocols for CPS and IoT
– Energy, real-time, and mobility management
– Design principles, methodologies, and tools for CPS and IoT
– Self-organization under severe resource constraints
– Applications and case studies of autonomic CPS and IoT

* Self-Organization and Organic Computing
– Self-organization principles and organic computing principles borrowed from
systems theory, control theory, game theory, decision theory, social
theories, biological theories, etc.
– Self-organization, emergent behavior, decentralized control, individual and
social/organizational learning, scalability, robustness, goal- and norm-
governed behavior, online self-integration for trustworthy self-organizing
and organic systems
– Infrastructures and architectures for self-organizing systems and organic
computing systems
– Applications and case studies for self-organization and organic computing

* Emerging Computing Paradigms: Cognitive Computing, Self-Aware Computing
– Advanced learning for cognitive computing such as meta-cognitive learning,
self-regulatory learning, consciousness and cognition in learning,
collaborative / competitive learning, and online / sequential learning
– Architectures, control, algorithmic approaches, instrumentation, and
infrastructure for cognitive computing and self-aware systems
– Cognitive computing and self-awareness in heterogeneous and decentralized
systems
– Applications and case studies for social networks, big data systems, deep
learning systems, games, and artificial assistants, cognitive robots, and
systems with self-awareness and self-expression

* Software Engineering for Autonomic Computing Systems: Architecture,
Specifications, Assurances
– Design methodology, frameworks, principles, infrastructures, and tools for
development and assurances for autonomic computing systems
– System architectures, services, components and platforms broadly applicable
for autonomic computing system engineering
– Goal specification and policies, modeling of service-level agreements,
behavior enforcement, IT governance, and business-driven IT management
– Applications and case studies for software engineering approaches for
autonomic computing systems

In addition to fundamental results ICAC is also interested in applications and
experiences with prototyped or deployed systems solving real-world problems in
science, engineering, business, or society. Typical application areas for ICAC
are autonomous robotics, cloud computing, cyber-physical systems, data centers,
dependable computing, industrial internet / industry 4.0, internet of things,
mobile computing, service-oriented systems, smart buildings, smart city,
smart grid / energy management, smart factory, smart user interfaces,
space applications, and traffic management.

This year a doctoral symposium will be organized as part of ICAC.
For more information see
http://icac2016.uni-wuerzburg.de/calls/doctoral-symposium/

All papers must represent original and unpublished work that is not currently
under review. Submissions are required to mark at least one topic area.
Papers will be reviewed by at least three PC members including at least two
having specific domain expertise concerning the indicated
main research topics and judged on originality, significance, interest,
correctness, clarity, and relevance to the broader community. At least one author
of each accepted paper is expected to attend the conference.

Papers can be submitted in one of the following three categories with different
acceptance criteria for each category:

* Full research papers limited to 10 pages (double column, IEEE format)
* Experience papers limited to 8 pages (double column, IEEE format)
* Short papers limited to 6 pages (double column, IEEE format)

Full and experience research papers are strongly encouraged to report on
experiences, measurements, user studies, and provide an appropriate quantitative
evaluation if at all possible. Short papers can either be work in progress,
or position and challenge papers that motivate the community to address
new challenges. See the conference website for format instructions
(http://icac2016.uni-wuerzburg.de/calls/instructions-to-authors/).
Papers must be submitted electronically in PDF format through the
ICAC’2016 submission site (https://easychair.org/conferences/?conf=icac2016).

There will be a BEST PAPER AWARD for the full research paper category and
it is panned that a selection of the best papers of the full research paper
category will be invited to submit an extended version of their contribution
for an ICAC 2016 SPECIAL ISSUE after the conference.

___________________________________________________________________

ORGANIZATION

General Chairs
Samuel Kounev, University of Wuerzburg, Germany

Program Committee Co-Chairs
Holger Giese, Hasso Plattner Institute, Germany
Jie Liu, Microsoft Research, Redmond, USA

Workshop Chair
Lydia Chen, IBM Zurich, Switzerland

Publicity Co-Chairs
Giacomo Cabri, Universita di Modena e Reggio Emilia, Italy
Javier Camara, Carnegie Mellon University, Pittsburgh, USA
Nikolas Herbst, University of Wuerzburg, Germany
Jianguo Yao, Shanghai Jiao Tong University, China

Finance Chair
Philippe Lalanda, University of Grenoble, France

Proceedings Chair
Daniel Gmach, HP Labs, USA

Poster and Demo Chair
Stephanie Chollet, Grenoble INP Esisar/LCIS, France

Local Arrangements and Web Chair
Lukas Ifflaender, University of Wuerzburg, Germany

Doctoral Symposium Chair
Christian Becker, University of Mannheim, Germany
Evgenia Smirni, College of William and Mary, USA
___________________________________________________________________

PROGRAM COMMITTEE
Tarek Abdelzaher, University of Illinois at Urbana-Champaign, USA
Artur Andrzejak, Heidelberg University, Germany
Luciano Baresi, DEIB – Politecnico di Milano, Italy
Jacob Beal, BBN Technologies, USA
Christian Becker, University of Mannheim, Germany
Kirstie Bellman, The Aerospace Corporation, USA
Nelly Bencomo, Aston University, UK
Giacomo Cabri, Universita di Modena e Reggio Emilia, Italy
Lydia Chen, IBM Zurich, Switzerland
Lucy Cherkasova, HP Labs, USA
Elisabetta Di Nitto, Politecnico di Milano, Italy
Ada Diaconesco, Telecom ParisTech, France
Schahram Dustdar, TU Wien, Austria
Lukas Esterle, Universitaet Klagenfurt, Austria
Kurt Geihs, Universitaet Kassel, Germany
Rean Griffith, VMWare, USA
Yuan He, Tsinghua University, China
Jeff Kephart, IBM T.J. Watson Research Center, USA
Xenofon Koutsoukos, Vanderbilt University, USA
Michael Kozuch, Intel, USA
Philippe Lalanda, University of Grenoble, France
Peter Lewis, Aston University, UK
Xiaolin Li, University of Florida, USA
Marin Litoiu, York University, Canada
Xue Liu, McGill University, Canada
Chenyang Lu, Washington University at St. Louis, USA
Ying Lu, University of Nebraska – Lincoln, USA
Martina Maggio, Lund University, Sweden
Sam Malek, George Mason University, USA
Julie McCann, Imperial College London, UK
Ole J. Mengshoel, Carnegie Mellon University, USA
Arif Merchant, Google, USA
Christian Müller-Schloer, Leibniz Universitaet Hannover, Germany
Hausi A. Müller, University of Victoria, Canada
Miroslav Pajic, Duke University, USA
Gian Pietro Picco, University of Trento, Italy
Dario Pompili, Rutgers University, USA
Eric Rutten, NRIA Grenoble Rhône-Alpes, France
Hartmut Schmeck, Karlsruhe Institute of Technology, Germany
Onn Shehory, IBM Research Haifa, Israel
Mike Smit, Dalhousie University, Canada
Christopher Stewart, Ohio State University, USA
Ladan Tahvildar, Waterloo University, Canada
Sven Tomforde, Universitaet Augsburg, Germany
Bhuvan Urgaonkar, Penn State, USA
Di Wang, Microsoft Research, USA
Danny Weyns, Linnaeus University, Sweden
Zheng Zhang, Rutgers University, USA
Xiaoyun Zhu, Futurewei Technologies, USA

FORTE 2016 Call for Papers

36th IFIP International Conference on Formal Techniques for Distributed Objects, Components and Systems

http://forte2016.discotec.org

Part of the DisCoTec 2016 event

http://2016.discotec.org/index.php

6-9 June 2016, Aquila Atlantis Hotel, Heraklion, Crete

FORTE 2016 is a forum for fundamental research on theory, models,

tools, and applications for distributed systems. The conference

solicits original contributions that advance the science and

technologies for distributed systems, with special interest in the

areas of:

– service-oriented, ubiquitous, pervasive, grid, cloud, and mobile

computing systems;

– object technology, modularity, component- and model-based design;

– software reliability, availability, and safety;

– security, privacy, and trust in distributed systems;

– adaptive distributed systems, self-stabilization;

– self-healing/organizing;

– verification, validation, formal analysis, and testing of the above.

Contributions that combine theory and practice and that exploit formal

methods and theoretical foundations to present novel solutions to

problems arising from the development of distributed systems are

encouraged. FORTE covers distributed computing models and formal

specification, testing and verification methods. The application

domains include all kinds of application-level distributed systems,

telecommunication services, Internet, embedded and real-time systems,

as well as networking and communication security and reliability.

Main topics of interest

Topics of interest include but are not limited to:

– Languages and semantic foundations: new modeling and language

concepts for distribution and concurrency, semantics for different

types of languages, including programming languages, modeling

languages, and domain-specific languages; real-time and probability

aspects;

– Formal methods and techniques: design, specification, analysis,

verification, validation, testing and runtime verification of

various types of distributed systems including communications and

network protocols, service-oriented systems, adaptive distributed

systems, cyber-physical systems and sensor networks;

– Foundations of security: new principles for qualitative and

quantitative security analysis of distributed systems, including

formal models based on probabilistic concepts;

– Applications of formal methods: applying formal methods and

techniques for studying quality, reliability, availability, and

safety of distributed systems;

– Practical experience with formal methods: industrial applications,

case studies and software tools for applying formal methods and

description techniques to the development and analysis of real

distributed systems.

Important dates:

Abstract submission: February 1, 2016​

Paper submission: February 8, 2016

Notification of acceptance: March 21, 2016

Camera-ready version: April 4, 2016

Early registration: May 9, 2016

Conference and workshops: June 6-9, 2016

Invited speaker

Catuscia Palamidessi (INRIA, France)

Submission and publication

Contributions must be written in English and report on original,

unpublished work, not submitted for publication elsewhere (cf. IFIP’s

codes of conduct). The submissions must be prepared using Springer’s

LNCS style. Submissions not adhering to the specified constraints may

be rejected without review. Papers can be submitted electronically in

pdf via the FORTE’16 interface of the EasyChair system.

We solicit four kinds of submissions:

– Full papers (up to 15 pages): Describing thorough and complete

research results, tools or experience reports.

– Short papers (up to 7 pages): Describing research results that are

not fully developed, or manifestos, calls to action, personal views

on FORTE related research, on the current state of the art, or on

prospects for the years to come.

– Tool demonstration papers (up to 7 pages): focus on the usage

aspects of tools. Theoretical foundations and experimental

evaluation are not required, however, a motivation as to why the

tool is interesting and significant should be provided. Papers may

have an appendix of up to 5 additional pages with details on the

actual demonstration.

– Posters (up to 3 pages): Students can submit descriptions of posters

that will be presented at the conference during a students poster

session. Neither the descriptions or the posters will be published

in the proceedings.

Each paper will undergo a peer review of at least 3 anonymous

reviewers. The conference proceedings will be published by Springer in

the LNCS Series. The best papers will be invited after the conference

to contribute to a special issue of a top-level journal.

Program Committee Chairs

Elvira Albert, Complutense University of Madrid, Spain

Ivan Lanese, University of Bologna/INRIA, Italy

Program Committee

Erika Abraham, RWTH Aachen University, Germany

Gul Agha, University of Illinois at Urbana-Champaign, USA

Ahmed Bouajjani, LIAFA, University Paris Diderot, France

Frank De Boer, CWI, the Netherlands

Lars-Ake Fredlund, Universidad Politécnica de Madrid, Spain

David Frutos Escrig, Universidad Complutense, Spain

Stefania Gnesi, ISTI-CNR, Italy

Kim Guldstrand Larsen, Aalborg University, Denmark

Bart Jacobs, Katholieke Universiteit Leuven, Belgium

Einar Broch Johnsen, University of Oslo, Norway

Antónia Lopes, University of Lisbon, Portugal

Massimo Merro, University of Verona, Italy

Peter Olveczky, University of Oslo, Norway

Luca Padovani, Università di Torino, Italy

Anna Philippou, University of Cyprus, Cyprus

Arnd Poetzsch-Heffter, University of Kaiserslautern, Germany

Emilio Tuosto, University of Leicester, UK

Kostis Sagonas, Uppsala University, Sweden

Alexandra Silva, University College London, UK

Jean-Bernard Stefani, INRIA, France

Mahesh Viswanathan, University of Illinois Urbana-Champaign, USA

Call for Papers

DREAMCloud 2016
2nd International Workshop on Dynamic Resource Allocation and Management
in Embedded, High Performance and Cloud Computing

Jan 19th 2016
Co-Located with HiPEAC 2016
Prague, Czech Republic
https://www.hipeac.net/events/activities/7316/dreamcloud/

 

– Paper submission deadline:  November 20, 2015 (EXTENDED)
Jointly organised by the DreamCloud and EXCESS projects.

——————————————————————————–

DREAMCloud is a workshop aiming to encourage technical and scientific exchanges
between senior academics, young researchers and industrialists in the area of
dynamic resource management in embedded, high performance and cloud computing.
It has strong emphasis on performance predictability and energy
efficiency, which are the key issues addressed by the DreamCloud and
EXCESS projects.
It aims to foster cooperation across the different domains by emphasising the
latest trends bringing together the respective research communities:

– embedded systems are increasingly complex, having to cope with dynamic
workloads, and using multiprocessor and communication-centric platforms, while
fulfiling strict timing and energy requirements;

– high-performance and cloud computing critically need to address fundamental
problems in energy efficiency and performance predictability, despite having
little or no a priori knowledge about their workloads.

The second DREAMCloud Workshop will be co-located with the HiPEAC 2016
Conference in Prague, Czech Republic (https://www.hipeac.net/2016/prague/).

TOPICS OF INTEREST

– dynamic resource allocation and management algorithms and heuristics for
time-predictable and performance-predictable systems

– dynamic resource allocation and management algorithms and heuristics
targeting energy-efficiency

– operating system and virtualisation technologies implementing dynamic
resource allocation and management (task allocation, task migration, context
management)

– dynamic resource allocation of on-chip and off-chip interconnects (routing,
buffer allocation)

– dynamic management of memory hierarchies and storage (time-predictable memory
controllers, scratchpads, file systems)

– dynamic hardware reconfiguration to support dynamic resource management
(hardware-assisted dynamic scheduling and allocation)

– approaches to energy-efficient computing paradigms for emerging many-core
architectures

– energy execution models

– energy-aware compiler optimizations and runtime support

– specification languages and environments (workload characterisation)

– system monitoring (workload monitoring, platform monitoring, energy
monitoring)

– verification and evaluation techniques (simulation, analytical models)

– benchmarks for dynamic resource allocation in embedded, high performance and
cloud computing

The workshop is organised by the EU-funded DreamCloud and EXCESS project
consortia, which have both started in September 2013 and are addressing some
of the topics listed above.
The overall goal of the workshop, however, is to assess the most relevant
research contributions and industrial needs in this area, therefore
contributions from
outside of the consortia are extremely welcome and will be given
preference in the final programme.

IMPORTANT DATES

– Submission: 12th November, 2015, extended to 20th November, 2015
– Notification: 15th December, 2015
– Final Version: 5th January, 2015
– Workshop 19th January, 2016

SUBMISSION

Authors are invited to submit contributions as maximum 8 page papers in IEEE
format. Contribution(s) have to be submitted electronically through EasyChair:
https://easychair.org/conferences/?conf=dreamcloud2016

All accepted papers will be published in arXiv’s Computing Research
Repository (CoRR).

A selection of the best papers may be considered for publication as a journal
special issue after the event.

ORGANISERS

Leandro Soares Indrusiak – University of York, UK
Alexey Cheptsov – High Performance Computing Center Stuttgart (HLRS), DE

Technical Program Committee

Neil Audsley – University of York, UK
Luciano Copello Ost – University of Leicester, UK
Alexey Cheptsov – High Performance Computing Center Stuttgart, DE
Piotr Dziurzanski – University of York, UK
Abdoulaye Gamatie – LIRMM, FR
Christoph Kessler – Linköping University, SE
Amit Kumar Singh – University of York, UK
Borislav Nikolic – Polytechnic Institute of Porto, PT
Raj Patel – RheonMedia, UK
Paul Renoud-Goud, Chalmers University of Technology, SE
Gilles Sassatelli – LIRMM, FR
Fridtjof Siebert – aicas, DE
Bjoern Saballus – Bosch, DE
Leandro Soares Indrusiak – University of York, UK
Philippas Tsigas – Chalmers University of Technology, SE

====================================================================
                             HARSH 2016
    Workshop on Highly-Reliable Power-Efficient Embedded Designs

                          CALL FOR PAPERS
====================================================================
    Our apologies if you receive multiple copies of this message
====================================================================

March 12th 2016, Barcelona (Spain)
In conjunction with HPCA 2016, CGO 2016, and PPoPP 2016

Website: http://www.harsh-workshop.org/

===========================
CALL FOR PAPERS
===========================

HARSH 2016 will provide a unique forum for the discussion of the
challenges in the design and operation of harsh environment-capable
embedded processors.

Nowadays, embedded chips are deployed almost everywhere, from mobile
phones to on-board electronics in automobiles and satellites.
Different from conventional microprocessor designs, the operation
conditions of embedded processors are severely constrained by the
environment. For example, in aerospace applications, the computer
installed on Mars rover "Curiosity" has to tolerate extreme space
radiation and temperatures, operate at low power, and provide enough
computation capability to perform mission-critical tasks. Embedded
designs for Unmanned Aerial Vehicles (UAVs) also encounter extremely
challenging design requirements. Despite their tight power budget,
UAV chips demand significant throughput for real-time high-speed
image processing. In the context of oil and gas exploration and
extraction, embedded processors can be found even on the drill string
itself, to process sensor inputs in real time while withstanding high
temperatures and humidity levels.

To guarantee reliability across these drastically diverse
environments, the design and operation of embedded processors should
not be solely confined to the chip but traverse different layers in
the computing system, involving firmware, operating system,
applications, as well as power management units and communication
interfaces. The goal of HARSH 2016 is to facilitate the exchange of
the latest ideas, insights, and knowledge related to all critical
aspects of new-generation harsh environment-capable embedded
processors, including micro-architectural approaches, cross-stack
hardware/software techniques, and emerging challenges and
opportunities. We hope to attract a group of interdisciplinary
researchers from academia, industry, and government research labs.

In addition to the presentation of selected paper submissions,
keynote speakers will be invited to kick-off the workshop sessions
and a "Best Paper" award will be presented at the conclusion of the
workshop. To encourage discussion between participants, HARSH 2016
will organize dedicated programs for discussion between presenters
and the audience.

===========================
TOPICS
===========================

Topics of interest include but are not limited to:

(1) Architecture design and implementation for highly-reliable
    power-efficient embedded processors:
    - Architectural approaches for reliability assurance under
      very-low power budgets.
    - Availability, soft-error tolerance and recovery issues.
    - Highly-reliable cache/memory hierarchies.
    - Massive heterogeneous processing capabilities.
    - Power management techniques.
    - Very-low power, reliable real-time processing.
    - Specialized accelerator architectures and unique designs.
    - Reusable and/or reconfigurable embedded designs.
    - Packaging and cooling.

(2) Cross-stack hardware/software techniques:
    - Cross-stack approaches for reliability assurance under
      very-low power budgets.
    - Reliability- and power-aware operating systems, compilers,
      workload managers, firmware and other software.
    - Workload analysis and optimization for reliable low-power
      embedded systems.

(3) Applications:
    - Aerospace: unmanned aerial vehicles (UAVs), planetary rovers
      and space probes, satellites, avionic systems, etc.
    - Medical support: lifesaving monitors, portable medical devices,
      high-end imaging systems, etc.
    - Oil and gas exploration and extraction: unmanned underwater
      vehicles (UUVs), measurement while drilling (MWD), logging
      while drilling (LWD), etc.
    - Aerial surveillance.
    - Disaster search, rescue, and relief.
    - Novel applications for highly-reliable low-power embedded
      chips.

===========================
SUBMISSIONS
===========================

Papers reporting original research results pertaining to the above
and related topics are solicited. Full paper manuscripts must be in
English of up to 6 pages (using the IEEE two-column format). The
on-line submission site is EasyChair. If web submission is not
possible, please contact the program co-chairs for alternate
arrangements.

To submit regular papers to the workshop, please visit:
http://www.harsh-workshop.org/submissions

If you have questions regarding submission, please contact us:
info@harsh-workshop.org

Important Dates:

  - Submission deadline: Jan 22, 2016
  - Notification of acceptance: Feb 8, 2016
  - Final paper submission: Feb 26, 2016
  - Workshop date: Mar 12, 2016

===========================
ORGANIZING COMMITTEE
===========================

  - Augusto Vega (IBM Research)
  - Xuan (Silvia) Zhang (Washington University in St. Louis)
  - David Brooks (Harvard University)
  - Alper Buyuktosunoglu (IBM Research)
  - Pradip Bose (IBM Research)