Alhamdulillah. I am relief….today received a good news. My publication in IET Power Electronics was accepted. A review was quite though with 6 reviewers that comments on the novelty of the proposed multi level topology.
Since 2018, that research topic is blooming with a lot of topologies came year after year. The area was to search for a good and well-balanced topology that can generate a high number of output voltage level but at the same time has a low number of the power switch and low total standing voltage. The big challenge here is to have a low Total standing voltage.
Another comments is on the applications of the proposed topology since the topology use asymmetrical dc sources.
IET Power Electronics is is Q2. So for this year (till March 2021 and more will come), i have published:
- IEEE Access – Q1
- International Journal on Circuit Theory and Application – Q3
- IET Power Electronics – Q2
- IJPEDS -SCOPUS